POWER2 instruction cache unit

Introduction IBM introduced the POWER-based RISC System/6000@ (RS/6000) workstation in February of 1990. This system was well received in the industry and helped IBM capture a sizable share of the workstation market. The POWER2TM processor goals were to build on the strengths of the original POWER design and to overcome its shortcomings. The POWER and POWER2 systems partition instruction processing across three units: the instruction cache unit (ICU), the fixed-point unit (FXU), and the floating-point unit (FPU). This paper describes the overall organization of the POWER2 ICU, as well as the improvements over the previous design. Figure 1 is a block diagram of the POWER2 ICU. The primary functions of the ICU are the following: